Saleh Mesbah Saleh Abdelhafeez - Qatar.

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Faculty members

saleh mesbah saleh abdelhafeez

Associate Professor

College of Computer

Department of Computer Engineering

Personal data

Scientific qualifications

Research interests

Published research

Reconfigurable FIFO memory circuit for synchronous and asynchronous communication (2021-01-12)
Design of Memory Alias Table based on the SRAM 8T-Cell (2022-04-09)
Programmable Feedback Shift Register (2023-03-11)
A novel self-timing CMOS first-edge capture circuit for on-chip communication systems (2023-06-21)
A One-Cycle Asynchronous FIFO Queue Buffer Circuit (2020-01-01)
Cost-Effective Winner-Take-All Approach for Comparing Multi-Output Neural Networks (2026-01-01)
Alias Table Memory Circuit for Register Renaming Unit (2019-01-01)
A One-Cycle FIFO Buffer for Memory Management Units in Manycore Systems (2019-01-01)
A comparison-free sorting algorithm on CPUs and GPUs (2018-11-01)
High-Speed Low-Power Flash ADC Architecture Using Switched-Capacitor Positive Feedback Comparator and Parallel Single-Gate Encoder (2018-06-01)
Sorting-free digital median filter for SOCs (2017-08-01)
An Efficient O(N) Comparison-Free Sorting Algorithm (2017-06-01)
A mixed analog-digital fast Hamming-weight filtering circuit using switched-capacitor arrays (2015-04-01)
A Comparison-Free Sorting Algorithm (2014-01-01)
Scalable Digital CMOS Comparator Using a Parallel Prefix Tree (2013-11-01)
High-speed and low-power scalable Hamming weight comparator based on a non-weighted switched-capacitor array (2013-06-01)
A Gigahertz Digital CMOS Divide-by-N Frequency Divider Based on a State Look-Ahead Structure (2011-12-01)
A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic (2011-06-01)
CMOS Eight-Transistor Memory Cell for Low-Dynamic-Power, High-Speed Embedded SRAM (2008-10-01)
High-speed digital CMOS divide-by-N frequency divider (2008-01-01)
A low-power CAM using a 12-transistor design cell (2007-01-01)
Low-power content-addressable memory with read/write and matched mask ports (2007-01-01)
HIGH-PERFORMANCE AES DESIGN USING A PIPELINED STRUCTURE OVER GF((2⁴)²) (2007-01-01)
A high-performance VLSI priority encoder using the Zstandard CMOS library (2006-08-01)
VLSI modified architecture for reduced symmetric fuzzy singleton set and its applications (1996-01-01)
A fast and cost-effective integer restoring division hardware (2024-04-01)
A novel methodology for reducing voltage drop at the core of IC chips (2007-05-01)
Cost-Effective Winner-Take-All Approach for Comparing Multi-Output Neural Networks (2026-01-01)
Programmable Feedback Shift Register (2023-08-01)
A novel self-timing CMOS first-edge capture circuit for on-chip communication systems (2023-07-01)
Reconfigurable FIFO memory circuit for synchronous and asynchronous communication (2021-04-01)
A One-Cycle Asynchronous FIFO Queue Buffer Circuit (2020-04-01)
A One-Cycle FIFO Buffer for Memory Management Units in Manycore Systems (2019-07-01)
A fast and cost-effective integer restoring division hardware (2024-05-01)
Design of Memory Alias Table based on the SRAM 8T-Cell (2022-08-01)
Alias Table Memory Circuit for Register Renaming Unit (2019-06-01)
A comparison-free sorting algorithm on CPUs and GPUs (2018-11-01)
High-Speed Low-Power Flash ADC Architecture Using Switched-Capacitor Positive Feedback Comparator and Parallel Single-Gate Encoder (2018-06-01)
Sorting-free digital median filter for SOCs (2017-08-01)
An efficient O(N) comparison-free sorting algorithm (2017-06-01)
A comparison-free sorting algorithm (2015-04-16)
A mixed analog–digital fast hamming-weight filtering circuit using switched-capacitor arrays (2015-02-11)
Scalable digital CMOS comparator using a parallel prefix tree (2013-10-07)
High-speed and low-power scalable Hamming weight comparator based on a non-weighted switched-capacitor array (2013-06-01)
A double data rate 8T-cell SRAM architecture for system-on-chips (2012-12-01)
A gigahertz digital CMOS divide-by-N frequency divider based on a state look-ahead structure (2011-12-01)
On-chip jitter measurement architecture using a delay-locked loop with vernier delay line, up to the order of giga hertz (2011-10-04)
A shadow dynamic finite state machine for branch prediction: An alternative for the 2-bit saturating counter (2011-06-29)
A digital CMOS parallel counter architecture based on state look-ahead logic (2011-06-01)
A new high-speed SAR ADC architecture (2010-12-01)
CMOS eight-transistor memory cell for low-dynamic-power high-speed embedded SRAM (2008-10-01)
High-speed digital CMOS divide-by-N frequency divider (2008-09-19)
High performance AES design using pipelining structure over GF((2 4) 2) (2007-12-01)
A low-power CAM using a 12-transistor design cell (2007-12-01)
A novel methodology for reducing the power supply voltage drop at the core of IC'S chips (2007-06-18)
Low-power content-addressable memory with read/write and matched mask ports (2007-01-01)
A VLSI High-Performance Priority Encoder Using Standard CMOS Library (2006-01-01)
VLSI modified architecture for reduced symmetric fuzzy Singleton set and its applications (1996-01-01)

Teaching materials